Big LED Screen
The Big LED Screen
- Dimensions (in pixels) are 128 by 48
- Originally controlled by a 386; mobo is shot.
- The 386 connects via ISA to a "buffer board" which looks to be a memory buffer and power conditioner.
- The buffer board stores data into a couple memory chips, which are then accessible to the daughterboards which drive the actual LEDs.
- There are four daughterboards, in two chains of length two. Each of these daughterboards is connected to a single "section" of LEDs (ie: there are four big "sections" of LEDs). Each daughterboard runs a section of 32 by 48 pixels.
As of 2009-01-28 I am potentially leaving things connected inside it as I work on it. If you want to work on it, please make sure you either check with me or disconnect the things I added before turning it on. Thanks! --Shkoo 10:04, 28 January 2009 (PST)
Boring. Broken. Did I mention boring?
Tonight (2008-12-30) I worked from the backend up a bit, but eventually gave up. I then moved to the ISA frontside and worked down, which was far more productive.
The device appears to sit at ISA IO ports 0x180 through 0x183. The addresses are decoded by U51 (74688 comparator), which then hits the OE2 on U52-19 (74541 driver iirc). This is then used to feed U53 and U54 (both 74574 D-flip-flops). These appear to be there to combat fan-out. I'm not entirely certain where these go, but it seemed like they were going into the RAMs.
The low bits of the ISA address selection sit on the rightmost two pins on the top row of the header, SA1 and SA0, in that order (Just hook the connector up and use the multimeter if that's nonsensical). I haven't traced them through yet; I was in the middle of it when my time ran out. They look to run over to the empty chip socket on the right side of the board. Most traces tend to terminate at this chip socket, so most likely we won't be able to use the display logic on the buffer board.
The daughterboards each have qty 3 UCN5832A (File:Ucn5832.pdf) 32-bit shift registers (for a total of 96 bits) which drive an array of 32 by 48 pixels (for a total of 1536). The theory is the other end of the LEDs are connected to 16 different power sources, making all the LEDs addressable (96 * 16 = 1536). (The shift register does a current sink)
The daughterboards receive serial based on the following:
- The long 10-pin pigtails are as follows:
1 - UCN-40 CLK (serial clock) 2 - GND 3 - UCN-4 STROBE (latch driver) 4 - GND 5 - UCN-2 SIN (serial in) 6 - GND 7 - UCN-3 GND 8 - GND 9 - GND
Pin 1 is marked red. When looking into the end of the connector, when the red-marked wire is on the left, odd pins are on top. So, the top left pin is pin 1.
The serial is daisy chained together. There are two sets of two daughterboards (four daughterboards total) with 3 shift registers on each daughterboard. So, each chain of shift registers includes 6 shift registers for a total of 192 bits per chain.
(The existing logic shifts out 200 bits instead of 192; we don't know why).
Looking at the sign doing STROBE: sequences 130us apart, within each sequence, 5 peaks @+5V, 4us each high, otherwise the signal is low.
Looking at CLK: We do a bunch of lcokign, the strobe, etc. 8 CLKs in 5us, entire process takes 125us, appx 200CLKs. This gives an input rate of 1.6MHz(!)
The shift register is rated for 3.3Mhz, so we could conceivably drive it faster than the 1.5Mhz that it's currently running.