Big LED Screen
The Big LED Screen
- Dimensions (in pixels) are 128 by 48
- Originally controlled by a 386; mobo is shot.
- The 386 connects via ISA to a "buffer board" which looks to be a memory buffer and power conditioner.
- The buffer board stores data into a couple memory chips, which are then accessible to the daughterboards which drive the actual LEDs.
- There are four daughterboards, in two chains of length two. Each of these daughterboards is connected to a single "section" of LEDs (ie: there are four big "sections" of LEDs). Each daughterboard runs a section of 32 by 48 pixels.
As of 2009-01-28 I am potentially leaving things connected inside it as I work on it. If you want to work on it, please make sure you either check with me or disconnect the things I added before turning it on. Thanks! --Shkoo 10:04, 28 January 2009 (PST)
Boring. Broken. Did I mention boring?
Tonight (2008-12-30) I worked from the backend up a bit, but eventually gave up. I then moved to the ISA frontside and worked down, which was far more productive.
The device appears to sit at ISA IO ports 0x180 through 0x183. The addresses are decoded by U51 (74688 comparator), which then hits the OE2 on U52-19 (74541 driver iirc). This is then used to feed U53 and U54 (both 74574 D-flip-flops). These appear to be there to combat fan-out. I'm not entirely certain where these go, but it seemed like they were going into the RAMs.
The low bits of the ISA address selection sit on the rightmost two pins on the top row of the header, SA1 and SA0, in that order (Just hook the connector up and use the multimeter if that's nonsensical). I haven't traced them through yet; I was in the middle of it when my time ran out. They look to run over to the empty chip socket on the right side of the board. Most traces tend to terminate at this chip socket, so most likely we won't be able to use the display logic on the buffer board.
The daughterboards each have qty 3 UCN5832A (File:Ucn5832.pdf) 32-bit shift registers (for a total of 96 bits) which drive an array of 32 by 48 pixels (for a total of 1536). The theory is the other end of the LEDs are connected to 16 different power sources, making all the LEDs addressable (96 * 16 = 1536). (The shift register does a current sink)
The daughterboards receive serial based on the following:
- The long 10-pin pigtails are as follows:
1 - UCN-40 CLK (serial clock) 2 - GND 3 - UCN-4 STROBE (latch driver) 4 - GND 5 - UCN-2 SIN (serial in) 6 - GND 7 - UCN-3 GND 8 - GND 9 - GND
Pin 1 is marked red. When looking into the end of the connector, when the red-marked wire is on the left, odd pins are on top. The keyed edge of the connector is also on top. The top left pin is pin 1.
Per Josh, the grounds do not need to be connected for now.
The serial is daisy chained together. There are two sets of two daughterboards (four daughterboards total) with 3 shift registers on each daughterboard. So, each chain of shift registers includes 6 shift registers for a total of 192 bits per chain.
- The 10-pin ports between the daughterboards (J3 and J2) are wired differently. J3 is:
1 - 2 - 3 - 4 - 5 - ground 6 - 7 - clock 8 - 9 - serial out (j2) / serial in (j3) 10 -
(The existing logic shifts out 200 bits instead of 192; we don't know why).
Looking at the sign doing STROBE: sequences 130us apart, within each sequence, 5 peaks @+5V, 4us each high, otherwise the signal is low.
The shift register is rated for 3.3Mhz, so we could conceivably drive it faster than the 1.5Mhz that it's currently running.
Plan of Nils
The short term plan is complete.
The arduino is hooked up to drive one of the chains consisting of two daughterboards on the right half of the sign. The software does not use the arduino framework; instead, it compiles with avrgcc. The arduino framework doesn't have enough processing power to run fast enough for this application.
Here are the pins that need to be connected other than power and ground:
- MOSI (PB3) - this sends serial data to the daughterboard
- SCK (PB5) - this sends lcock signal to the daughterboard
- PB1 - this should be connected to the latch/strobe signal from the old buffer board
- PB0 - this should be connected to the latch/strobe signal going to the daughterboard
- PD7 - this should be hooked up to the left side of one of the power sources on the buffer board through a voltage divider (and small capacitor to stabilize the signal) to bring the 15 volts down to 5 volts. Do not use the output of the power source, since it's not nearly as stable.
It uses the existing STROBE (latch) signal from the buffer board for timing, and reads the state of one of the buffer board's output powers to synchronize where in the sequence of 16 power sources. It captures the latch signal and re-emits it to the daughterboard.
It ignores the serial clock and serial data from the buffer board.
Unfortunately this has very little processor time to spare since it's spending all its time clocking out the serial data. We're probably limited to very basic patterns on here.
Get an atmel xmega based solution. It has 4 UARTs that we can use 3 of as following:
- Drive daughter board 1
- Drive daughter board 2
- Drive XBEE wireless chip for communication with the outside world so we don't have to deal with running wires through the case
We also need to control our own power, since it's really tough to synchronize based on the existing board's power so we get a bit of pixel leakage.
The xmega does DMA to its UARTs so we don't have to waste quite so much CPU time copying bytes out.
Unfortunately none of the atmel xmega series have DIP packages, so it's a bit tougher to breadboard them. TQFP 100 seems like the way to go.
If anyone wants to mess around with etching a pcb to support this solution (assuming tests on the short term solution go well), let me know. Otherwise I'll send it off to batchpcb, but that takes a few weeks. -nils