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<h1>Open Hardware for Secure Networks And Privacy (OHSNAP)</h1>
<h1>Open Hardware for Secure Networks And Privacy (OHSNAP)</h1>


This is the project page for OHSNAP, an open-source platform for building secure networks with a known root of trust.
This is the project page for OHSNAP, an open-source platform for building secure networks with a known hardware root of trust.


<h2>Motivation</h2>
<h2>Motivation</h2>
Line 18: Line 18:


<h2>Status</h2>
<h2>Status</h2>
<h3>May 8, 2021</h3>
* Continued exploration of threat vectors and possible mitigations.
* More links added to [[#Links to Resources|resource list]].
* Setting up [https://github.com/maqp/tfc Tinfoil Chat] as a realtime collaboration platform and exploration of secure methodologies.
* Setting up OpenBSD on various SBCs and virtual machines to evaluate its fitness for use.
<h3>April 3, 2021</h3>
<h3>April 3, 2021</h3>
<p>Identified three regimes for threat models, some concrete examples, and some hypothetical mitigations:</p>
<p>Identified three regimes for threat models, some concrete examples, and some hypothetical mitigations:</p>
Line 129: Line 135:
** [https://www.sfcircuits.com San Francisco Circuits]?
** [https://www.sfcircuits.com San Francisco Circuits]?
** [https://www.circuitlaunch.com CircuitLaunch]?
** [https://www.circuitlaunch.com CircuitLaunch]?
** [https://bayareacircuits.com Bay Area Circuits]?


<h2>Open Questions</h2>
<h2>Open Questions</h2>
Line 161: Line 168:
** [https://www.circuitlaunch.com CircuitLaunch]
** [https://www.circuitlaunch.com CircuitLaunch]
** [https://oshpark.com OSHPark]
** [https://oshpark.com OSHPark]
** [https://bayareacircuits.com Bay Area Circuits]
* '''Design tools'''
* '''Design tools'''
** [https://kicad.org KiCAD] - schematic capture and PCB layout
** [https://kicad.org KiCAD] - schematic capture and PCB layout
Line 168: Line 176:
** Wikipedia article on [https://en.wikipedia.org/wiki/Tamper-evident_technology Tamper Evident Technology]
** Wikipedia article on [https://en.wikipedia.org/wiki/Tamper-evident_technology Tamper Evident Technology]
** [https://media.ccc.de/v/36c3-10690-open_source_is_insufficient_to_solve_trust_problems_in_hardware#t=2848 "Open Source is insufficient to solve trust problems in hardware"] by Bunnie Huang (video presentation)
** [https://media.ccc.de/v/36c3-10690-open_source_is_insufficient_to_solve_trust_problems_in_hardware#t=2848 "Open Source is insufficient to solve trust problems in hardware"] by Bunnie Huang (video presentation)
** [https://dustidentity.com DustIdentity] embedded diamond nanocrystals for system ID
** [https://spectrum.ieee.org/tech-talk/computing/hardware/chaos-programmable-chips-secure PUFs] (Physically Unclonable Functions) created in silicon on the IC wafer
*** [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9380284 Paper] describing principle
** [https://sharps.org/wp-content/uploads/BECKER-CHES.pdf Stealthy Dopant-Level Hardware Trojans]

Revision as of 17:39, 12 May 2021

Open Hardware for Secure Networks And Privacy (OHSNAP)

This is the project page for OHSNAP, an open-source platform for building secure networks with a known hardware root of trust.

Motivation

Virtually all commercially-available networking equipment is proprietary and closed-source and cannot be independently verified to be free of malware. There have been documented cases of attackers – sometimes entire nation-states – physically modifying networking equipment and networkable devices in order to exfiltrate data and/or command & control otherwise-trusted systems. This leaves the average individual with little choice but to hope that their home network consists of and is secured by devices which do not phone home or contain other backdoors. Such a situation breaks the guarantee that the user's data and devices remain their sovereign property and instead places control into the hands of manufacturers and governments.

The goal of this project is to produce a completely open design and implementation for a network router with a verifiable root of trust. By making the hardware design, manufacturing process, and firmware and software stacks fully verifiable, it allows users to inspect the entire end-to-end flow of their data and to directly control some or all of the fabrication of the device in order to establish positive provenance.

Device Summary

The OHSNAP router will be a single-board computer running an open source firmware and OS. It will expose at least two Ethernet ports.

Design Goals

  • No closed-source firmware or software allowed anywhere in the stack
  • Implementation must be independently reproducible by third parties
  • Factory-made PCBs must be physically produced in the USA
  • Components should be as supplier-diversified as possible

Status

May 8, 2021

  • Continued exploration of threat vectors and possible mitigations.
  • More links added to resource list.
  • Setting up Tinfoil Chat as a realtime collaboration platform and exploration of secure methodologies.
  • Setting up OpenBSD on various SBCs and virtual machines to evaluate its fitness for use.

April 3, 2021

Identified three regimes for threat models, some concrete examples, and some hypothetical mitigations:

Threat Regime Example Scenario Possible Mitigations
During assembly Manufacturer tampering
  • PCB x-ray inspection
  • Translucent PCB substrate for visual inspection
  • Encase PCB in glitter epoxy
  • Tamper-evident paint
  • Apply heat-sensitive paint to PCB (detects soldering)
  • Vacuum-sealed enclosure with onetime-use pressure sensor
  • Serial numbers in ROM on ICs
  • Use common enough chip to reduce chance of silicon tampering
  • Pogo board testing
During transit to end-user Vendor/reseller tampering
Mail interdiction
Embed device in another device
At customer's install site Evil user tampering Live system intrusion detection (examples??)
Routine pogo board testing
Passive monitoring, e.g.,
  • audio/video monitoring of keypresses
  • RF leakage analysis
  • power analysis
 ???

March 27, 2021

Still looking for a non-BGA ARM processor that contains two Ethernet PHYs and has 0.5mm or greater lead pitch (for Voltera V-1 PCB production. We are now considering three options for design:

  • (A) Non-BGA ARM processor on a homemade mainboard [simplest but limited to non-gigabit speeds; may require SW porting]
  • (B) BGA ARM processor on a fabbed carrier board attached to a homemade mainboard [more complicated but higher performance and easier to source; may avoid SW porting]
    • E.g., NXP i.MX6SoloX
    • Unpopulated carrier board will need to be examined, probably via x-ray, after production
    • Carrier board reflow is still done by us
    • Still need to look for more ways to increase provenance
  • (C) Use an existing open source BGA-based project (e.g., Kosagi Novena) and modify it for trusted manufacturing [complexity likely between (A) and (B)]
    • Will still likely need a BGA carrier board from (B) but may reduce R&D costs of the project

Infrastructure

We’ll be setting up an IRC server in parallel to testing local deployment of the Element secure chat system.

March 20, 2021

In order to make forward progress on the hardware, we will choose OpenBSD as the initial operating system and an ARM-based architecture for the CPU. Users will be able to use their own ARM-compatible OS if they choose, including Linux and Plan9 (if software support is added).

We will first create a Software-Intent Proof of Concept (SIPoC), which will be an OpenBSD-based router running on a commercially available SBC. We may then want, as a Proof of Concept (PoC), to port the software stack to the Common Networks nodes at Noisebridge and begin deploying them across sites.

The first version of our custom hardware should be amendable to DIY manufacturing. This means no BGA parts. This severely restricts the list of CPUs/SoCs to older and lower-performance chips, limiting our capability to 100MBps initially. We'll expand this list as we discover more:

List of non-BGA ARM SoCs

March 13, 2021

  • Looking for secure communications platform for project collaboration. Element / Matrix look promising.
  • Possibly partner with CircuitLaunch for local hardware builds?

March 6, 2021

Initial meeting. Discussed range of HW/SW design choices.

Tentative Project Stages

  • SIPoC: OpenBSD router on commercial SBC
  • PoC: SW stack on Common Networks
  • Proto 1 build: Low-speed (10/100 Mbps) DIY version
  • Full build: 1 Gbps

Possible Design Choices for Future Versions

  • CPU
    • ARM/ARM64 SoC
    • RISC-V SoC
    • FPGA
    • Specifically no Intel/compatible architectures due to poor security record
  • OS / Application Code
    • OpenBSD
    • Qubes
    • Alpine Linux
    • Plan9
    • Custom FPGA code
  • Trusted manufacturers

Open Questions

  • How to offer root-of-trust guarantees to non-DIY customers

Meetings

We are currently (as of March 2021) meeting every Saturday at 14:00 PT (GMT-8) on the Noisebridge Jitsi video platform.

Links to Resources

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