Editing PS3
Jump to navigation
Jump to search
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
| Latest revision | Your text | ||
| Line 7: | Line 7: | ||
''I (too) have a 60 GB PS3 I'd be willing to donate. Was hoping to sell it, but maybe one of you fine coders would help me with a python project and/or iPhone app I'm working on... Regardless, I'll bring it by either this afternoon (June 18) or Tuesday (June 22).'' --[[User:Nthmost|Nthmost]] 23:23, 18 June 2009 (PDT) | ''I (too) have a 60 GB PS3 I'd be willing to donate. Was hoping to sell it, but maybe one of you fine coders would help me with a python project and/or iPhone app I'm working on... Regardless, I'll bring it by either this afternoon (June 18) or Tuesday (June 22).'' --[[User:Nthmost|Nthmost]] 23:23, 18 June 2009 (PDT) | ||
== Tools == | >== Tools == | ||
You really want to use llvm-gcc with the cellspu backend. Gcc kind of sucks. You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow. There is a distcc service available on the French GCC cluster if pony doesn't cut it. Talk to [[User:Dr jesus|Dr. Jesus]] for details. | You really want to use llvm-gcc with the cellspu backend. Gcc kind of sucks. You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow. There is a distcc service available on the French GCC cluster if pony doesn't cut it. Talk to [[User:Dr jesus|Dr. Jesus]] for details. | ||
| Line 15: | Line 15: | ||
# Programming the CBE is all the fun of concurrent programming combined with all the joy of paged memory. | # Programming the CBE is all the fun of concurrent programming combined with all the joy of paged memory. | ||
# The cell SPUs only have 256KiB of memory available. However, it's SRAM and it's bolted directly onto the logic. Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire. For many of the SIMD instructions, ''the load/store latency is close to the instruction latency.'' | # The cell SPUs only have 256KiB of memory available. However, it's SRAM and it's bolted directly onto the logic. Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire. For many of the SIMD instructions, ''the load/store latency is close to the instruction latency.'' | ||
# The SPUs have to share that space (the | # The SPUs have to share that space (the "local store") for instructions and data. | ||
# Ha ha no branch prediction. Unrolling, conditional load/store, and fucking with the linker is the norm. | # Ha ha no branch prediction. Unrolling, conditional load/store, and fucking with the linker is the norm. | ||
# But you do get a prefetcher. Cache lines are 128 bits, instructions are 32 bits, do the math. | # But you do get a prefetcher. Cache lines are 128 bits, instructions are 32 bits, do the math. | ||
| Line 28: | Line 28: | ||
# Yeah, about those floating point and integer division instructions... no. Sorry about the SPARC flashback. | # Yeah, about those floating point and integer division instructions... no. Sorry about the SPARC flashback. | ||
# You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong. | # You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong. | ||
---- | |||
<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;"> | |||
---- | |||
=[http://aqekuxeroja.co.cc This Page Is Currently Under Construction And Will Be Available Shortly, Please Visit Reserve Copy Page]= | |||
---- | |||
=[http://aqekuxeroja.co.cc CLICK HERE]= | |||
---- | |||
</div> | |||
== Applications == | == Applications == | ||