Difference between revisions of "Talk:DreamTeam/Reading"

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(new finds, mostly re fpga)
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Revision as of 08:26, 3 February 2017

2 Feb 2017


http://www.ijsret.org/pdf/120399.pdf "A Literature survey for Object Recognition using Neural Networks in FPGA"


https://kar.kent.ac.uk/14766/1/FPGA_based_Lorrentz_Howells.pdf "An FPGA based adaptive weightless Neural Network Hardware"


http://infoteh.etf.unssa.rs.ba/zbornik/2016/radovi/KST-1/KST-1-15.pdf "Analysis of Visible Light Communication System for Implementation in Sensor Networks"


http://www.ccs.fau.edu/~fuchs/pub/Exp_brain_res_slav.pdf "Anatomically constrained minimum variance beamforming applied to EEG"


https://www.ijsr.net/archive/v5i3/NOV162166.pdf "Based on Multi-FPGA Neuron Simulation Hardware Platform"


https://arxiv.org/pdf/1611.03000v1 "Bio-Inspired Spiking Convolutional Neural Network using Layer-wise Sparse Coding and STDP Learning"


https://arxiv.org/pdf/1606.00094v2 "Boda-RTC: Productive Generation of Portable, Efficient Code for Convolutional Neural Networks on Mobile Computing Platforms"


https://arxiv.org/pdf/1609.09671v1 "Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks"


https://arxiv.org/pdf/1606.04884v1 "cltorch: a Hardware-Agnostic Backend for the Torch Deep Neural Network Library, Based on OpenCL"


https://arxiv.org/pdf/1511.07376v2 "CNNdroid: GPU-Accelerated Execution of Trained Deep Convolutional Neural Networks on Android"


https://arxiv.org/pdf/1609.09296v1 "Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs"


https://arxiv.org/pdf/1511.06530v2 "Compression of Deep Convolutional Neural Networks for Fast and Low Power Mobile Applications"


https://arxiv.org/pdf/1608.04363v2 "Deep Convolutional Neural Networks and Data Augmentation for Environmental Sound Classification"


https://arxiv.org/pdf/1611.05128v1 "Designing Energy-Efficient Convolutional Neural Networks using Energy-Aware Pruning"


http://www.ijser.org/researchpaper/Digital-Hardware-Implementation-of-Artificial-Neural-Network-for-Signal-Processing.pdf "Digital Hardware Implementation of Artificial Neural Network for Signal Processing"


https://arxiv.org/pdf/1612.00694v1 "ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA"


http://ethesis.nitrkl.ac.in/4217/1/FPGA_implementation_of_artificial_neural_networks.pdf "FPGA IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS"


http://lab.fs.uni-lj.si/lasin/wp/IMIT_files/neural/doc/Omondi2006.pdf "FPGA Implementations of Neural Networks"


http://vast.cs.ucla.edu/sites/default/files/publications/ASP-DAC2017-1352-11.pdf "FPGA-based Accelerator for Long Short-Term Memory Recurrent Neural Networks"


http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.409.7533&rep=rep1&type=pdf "FPGA-TARGETED NEURAL ARCHITECTURE FOR EMBEDDED ALERTNESS DETECTION"


http://yann.lecun.com/exdb/publis/pdf/farabet-iscas-10.pdf "Hardware Accelerated Convolutional Neural Networks for Synthetic Vision Systems"


http://www.emo.org.tr/ekler/21eb0b827c09dd1_ek.pdf "HARDWARE IMPLEMENTATION OF A FEEDFORWARD NEURAL NETWORK USING FPGAs"


http://arxiv.org/pdf/1609.01287v1 "Holographic Entanglement Entropy"


http://jestec.taylors.edu.my/Vol%206%20Issue%204%20August%2011/Vol_6_4_411_428_AL%20JAMMAS.pdf "IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA"


http://www.nmr.mgh.harvard.edu/meg/pdfs/1993-Hamalainen-RMP.pdf "Magnetoencephalography - theory, instrumentation, and applications to non-invasive studies of the working human brain"


https://arxiv.org/pdf/1602.09046v1 "On Complex Valued Convolutional Neural Networks"


http://arxiv.org/ftp/arxiv/papers/1201/1201.4617.pdf "Photo-Thermal Neural Excitation by Extrinsic and Intrinsic Absorbers: A Temperature-Rate Model"


https://arxiv.org/pdf/1611.02450v1 "PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks"


https://arxiv.org/pdf/1511.05552v4.pdf "Recurrent Neural Networks Hardware Implementation on FPGA"


https://arxiv.org/pdf/1605.06402v1 "Ristretto: Hardware-Oriented Approximation of Convolutional Neural Networks"


https://arxiv.org/pdf/1511.06306v2 "Robust Convolutional Neural Networks under Adversarial Noise"


https://arxiv.org/pdf/1701.03400v2 "Scaling Binarized Neural Networks on Reconfigurable Logic"


https://homes.cs.washington.edu/~luisceze/publications/snnap-hpca-2015.pdf "SNNAP: Approximate Computing on Programmable SoCs via Neural Acceleration"


https://arxiv.org/pdf/1406.4729v4 "Spatial Pyramid Pooling in Deep Convolutional Networks for Visual Recognition"


https://arxiv.org/pdf/1612.04052v1 "Theory and Tools for the Conversion of Analog to Spiking Convolutional Neural Networks"


https://arxiv.org/pdf/1701.00485v2 "Two-Bit Networks for Deep Learning on Resource-Constrained Embedded Devices"


https://arxiv.org/pdf/1603.05201v2.pdf "Understanding and Improving Convolutional Neural Networks via Concatenated Rectified Linear Units"


https://arxiv.org/pdf/1606.05487v1 "YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights"