[Noisebridge-discuss] Anyone have a Darlington Transistor Array?

Seth David Schoen schoen at loyalty.org
Mon Oct 21 16:04:13 UTC 2013

```Tyler Freeman writes:

> Or know of another way to do letters on a 7-segment LED? Any help
> would be appreciated!

I remember binary numbers to 7-segment being an exercise for digital
logic synthesis, particularly for practice with Karnaugh maps

https://en.wikipedia.org/wiki/Karnaugh_map

which are a great technique for visualizing the underlying structure
of logic functions.

If you let ABCD be the four input bits and abcdefg be the seven
segments

https://en.wikipedia.org/wiki/File:7_segment_display_labeled.svg

ABCD abcdefg
0000 1111110
0001 0110000
0010 1101101
0011 1111001
0100 0110011
0101 1011011
0110 1011111
0111 1110000
1000 1111111
1001 1111011
1010 1110111
1011 0011111
1100 1001110
1101 0111101
1110 1001111
1111 1000111

then you have seven functions a(ABCD), b(ABCD), c(ABCD), d(ABCD),
e(ABCD), f(ABCD), g(ABCD) reading down the columns, each of which can
be represented from logic gates by drawing a Karnaugh map.  For
example, here is the map for the "a" segment:

\ AB 00 01 11 10
CD
00       1  0  1  1
01       0  1  0  1
11       1  1  1  0
10       1  1  1  1

This represents the four inputs ABCD and the required output a in
each case.  Then we can try to express this by drawing squares or
rectangles whose area is a power of two and that cover all of the
1s.  (Each rectangle represents a logical combination of the
input variables using AND; the overall synthesis combines these
using OR, which is called a "sum of products".  The idea is that the
output will be 1 if the input falls inside any of the rectangles
that were chosen to cover the map.)  One solution here is
CA'+CB+CD'+AD'+A'B'C'D'+A'BC'D+AB'C'D, which can be expressed as

(C AND (NOT A OR B OR NOT D))
OR
(A AND NOT D)
OR
(NOT A AND NOT B AND NOT C AND NOT D)
OR
(NOT A AND B AND NOT C AND D)
OR
(A AND NOT B AND NOT C AND D)

Repeating the process for each of the seven segments would give a
synthesis of the entire decoder using a whole bunch of logic gates.

I think the actual Karnaugh maps needed are as follows:

a
\ AB 00 01 11 10
CD
00       1  0  1  1
01       0  1  0  1
11       1  1  1  0
10       1  1  1  1

b
\ AB 00 01 11 10
CD
00       1  1  0  1
01       1  0  1  1
11       1  1  0  0
10       1  0  0  1

c
\ AB 00 01 11 10
CD
00       1  1  0  1
01       1  1  1  1
11       1  1  0  1
10       0  1  0  1

d
\ AB 00 01 11 10
CD
00       1  0  1  1
01       0  1  1  1
11       1  0  0  1
10       1  1  1  0

e
\ AB 00 01 11 10
CD
00       1  0  1  1
01       0  0  1  0
11       0  0  1  1
10       1  1  1  1

f
\ AB 00 01 11 10
CD
00       1  1  1  1
01       0  1  0  1
11       0  0  1  1
10       0  1  1  1

g
\ AB 00 01 11 10
CD
00       0  1  0  1
01       0  1  1  1
11       1  0  1  1
10       1  1  1  1

--
Seth David Schoen <schoen at loyalty.org>      |  No haiku patents
http://www.loyalty.org/~schoen/        |  means I've no incentive to