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Noisebridge wants a cluster of PS3 systems running Linux. See mailing list discussion here.

PS3 is up, goat.noise. Log in as noisebridge, guess the password. sudo for everyone. Tools in pony:~j.

The other PS3 is up, hippo.noise. Same configuration as goat. Dr jesus 13:10, 28 June 2009 (PDT)

I (too) have a 60 GB PS3 I'd be willing to donate. Was hoping to sell it, but maybe one of you fine coders would help me with a python project and/or iPhone app I'm working on... Regardless, I'll bring it by either this afternoon (June 18) or Tuesday (June 22). --Nthmost 23:23, 18 June 2009 (PDT)


You really want to use llvm-gcc with the cellspu backend. Gcc kind of sucks. You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow. There is a distcc service available on the French GCC cluster if pony doesn't cut it. Talk to Dr. Jesus for details.

Note that programming for the Cell requires making several significant architectural changes to any existing code base:

  1. Programming the CBE is all the fun of concurrent programming combined with all the joy of paged memory.
  2. The cell SPUs only have 256KiB of memory available. However, it's SRAM and it's bolted directly onto the logic. Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire. For many of the SIMD instructions, the load/store latency is close to the instruction latency.
  3. The SPUs have to share that space (the "local store") for instructions and data.
  4. Ha ha no branch prediction. Unrolling, conditional load/store, and fucking with the linker is the norm.
  5. But you do get a prefetcher. Cache lines are 128 bits, instructions are 32 bits, do the math.
  6. The SPEs like to eat in 128-bit chunks from their local store. This means you want to feed it packed data if your data is not in 128-bit quantities.
  7. But you do get intrinsics to swizzle and shuffle the data.
  8. However, the intrinsics follow the Altivec model.
  9. But you do have prefetcher hint intrinsics.
  10. However, the intrinsics contain potassium benzoate.
  11. A dedicated DMA core is available to page things in and out of each SPU. See the IBM SDK.
  12. Inter-SPU communication is possible via a hardware mechanism, but might not be a good idea depending on how much data is being pushed.
  13. Immediates are 18 bits.
  14. Yeah, about those floating point and integer division instructions... no. Sorry about the SPARC flashback.
  15. You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong.



It looks like we need about $300 to make one happen (PS3 40GB on ebay). We can get more than one though, the more the merrier.

adi is organizing donations. Please add yourself to this list if you'd like to contribute. Cash, check, or paypal accepted.

  • adi - $50
  • Josh - $50
  • David Molnar - $100
  • Charlie - $100 (and no not thinking about playing games with it either)
  • dpc - $75 (just to be different)
  • Jacob - $50